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Detail
Buku8-Bit Arithmetic and Logic Unit Design Verification Using Formal Method
Bibliografi
Author: PUTRA, TOMY MANDALA ; Bachri, Karel Octavianus (Advisor); Lukas (Advisor)
Topik: Higher Order Logic; Formal Method; ALU Verification; FPGA
Bahasa: (EN )    
Penerbit: Program Studi Teknik Elektro Fakultas Teknik Unika Atma Jaya     Tempat Terbit: Jakarta    Tahun Terbit: 2012    
Jenis: Theses - Undergraduate Thesis
Fulltext: Tomy Mandala Putra's Undergraduate Theses.pdf (2.56MB; 22 download)
Ketersediaan
  • Perpustakaan Pusat (Semanggi)
    • Nomor Panggil: FTE-2158
    • Non-tandon: tidak ada
    • Tandon: 1
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Abstract
A designed system must be tested in order to examine whether it contain error or bugs. Verification is a way to examine the design before it is fabricated to avoid wasting time and costs. The traditional way to verify a system is using exhaustive method, creating a full list of all possible inputs and outputs combinations and verify whether they are completely correct. The modern approach is using the formal method, which uses exhaustive algorithm and mathematical proving. In this thesis, a design of 8-bit Arithmetic and Logic Unit (ALU) is verified using the formal method. The designed ALU operations are AND, OR, XOR, and NOT for logical operation, addition, subtraction, and multiplication for arithmetic operation, and bit shifting operation. The verified design is simulated in ModelSim software and implemented on Spartan-3E FPGA board. The simulation and implementation, show that the designed ALU fulfills the specification and proves that formal method is able to verify the design efficiently.
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