Implementasi FFT pada FPGA dengan Algoritma dengan Algoritma Winograd Kecil  

Oleh:

Sutopo, Bambang

Jenis: Article from Journal - ilmiah nasional - tidak terakreditasi DIKTI
Dalam koleksi: SIGMA: Jurnal Sains dan teknologi vol. 5 no. 1 (Jan. 2002), page 1-8.
Topik: FFT; Winograd; FPGA

Ketersediaan

Perpustakaan Pusat (Semanggi) Nomor Panggil: SS25.3 Non-tandon: 1 (dapat dipinjam: 0) Tandon: tidak ada

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Isi artikel

Digital signal processing with FFT (Fast Fourier Transform) enhances the computation time compared to the processing with DFT (Discrete Fourier Transform). In signal processing algorithms, multipliers contribute dominant effect on the computation time. Winograd algorithm is an effort to reduce the number of multipliers in FFT processors, using cyclic bahavior in FFT algorithm. The advances in microelectronic technology, especially in FPGA (Field Programmable Gate Array), have made IC designing faster and easy to implement. Winograd algorithm is too sophisticated to implement in software, but has some advantages in hardware implementations. A four-point Winograd module for FFT has been developed in a XC4013 FPGA chip. The research shows that this module has 6 adder modules and one magnitude module, occupyng 78 % of the CLB in the chip. The computation time of this module is about 122 nanoseconds.

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