VLSI Architecture for Configurable and Low-Complexity Design of Hard-Decision Viterbi Decoding Algorithm  

Oleh:

Putra, Rachmad Vidya Wicaksana ; Adiono, Trio

Jenis: Article from Journal - ilmiah nasional - terakreditasi DIKTI
Dalam koleksi: Journal of ICT Research and Applications vol. 10 no. 1 (2016), page 57-75.
Topik: conditional adapter; configurable and low-complexity design; hard-decision Viterbi; optimized processing element; VLSI architecture.
Fulltext: 1351-9544-2-PB.pdf (958.36KB)

Isi artikel

Convolutional encoding and data decoding are fundamental processes in convolutional error correction. One of the most popular error correction methods in decoding is the Viterbi algorithm. It is extensively implemented in many digital communication applications. Its VLSI design challenges are about area, speed, power, complexity and configurability. In this research, we specifically propose a VLSI architecture for a configurable and low-complexity design of a hard-decision Viterbi decoding algorithm. The configurable and low-complexity design is achieved by designing a generic VLSI architecture, optimizing each processing element (PE) at the logical operation level and designing a conditional adapter. The proposed design can be configured for any predefined number of trace-backs, only by changing the trace-back parameter value. Its computational process only needs N + 2 clock cycles latency, with N is the number of trace-backs. Its configurability function has been proven for N = 8, N = 16, N = 32 and N = 64. Furthermore, the proposed design was synthesized and evaluated in Xilinx and Altera FPGA target boards for area consumption and speed performance.

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