Detail A 12b 10MS/s 18.9fJ/conversion-step sub-radix-2 SAR ADC   Oleh:  Kwuang-Han Chang ; Chih-Cheng Hsieh Jenis: Article from Proceeding Dalam koleksi: 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 25-27 April 2016 (ada di IEEE Explore), page 1-4. Fulltext: 07482524.pdf (268.0KB) Isi artikel This paper presents a 12b SAR ADC with segmented sub-radix-2 DAC and embedded digital calibration. The dither-based calibration with LMS adaptive filter is implemented to track the optimum bit-weights for compensation of DAC mismatch. Mid-threshold comparison switching procedure is proposed to tolerate both-side settling error by equalizing the up and down DAC transition voltage during SAR conversion. The prototyped SAR ADC achieves an FoM of 18.9fJ/conversion-step at 10MS/s and 1V supply. The ADC core and digital calibration part occupies an area of 0.05mm2 and 0.04mm2 in 90nm CMOS, respectively. Index Terms —SAR ADC, LMS, redundancy, capacitor mismatch, digital calibration. Opini Anda Klik untuk menuliskan opini Anda tentang koleksi ini! Kembali

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