Perbandingan Antara Floating - Point Execution Unit RS / 6000 dan I860  

Oleh:

Kartawidjaja, Maria Angela

Jenis: Article from Journal - ilmiah nasional - tidak terakreditasi DIKTI - atma jaya
Dalam koleksi: Metris: Jurnal Mesin, Elektro, Industri dan Sains vol. 6 no. 4 (Dec. 2005), page 230-236.
Topik: Pipelining; Superscalar; VLIW.
Fulltext: Maria A. Kartawidjaja - Bernard.pdf (5.83MB)

Isi artikel

To improve the performance of computer systems current microprocessors utilize instruction-level parallelism by a multi-stage instruction pipeline and by the superscalar or the Very Long Instruction Word (VLIW) technique. In superscalar and VLIW processors more than a single instruction can be issued to the execution units per cycle. This article compares the time required to execute floating-point instructions in terms of dock cycle between mo machines, an IBM RS/6000 and I860 The former is a superscalar machine and the latter is a VLIW machine We consider multiply-add instruction as our test case. We conclude that in RS/6000 machine less clock cycle is required if there is an interdependency between the operands of the instruction. On contrary, in I860 machine less clock cycle is required if the operands of the instruction are independent.

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