Hardware Implementation of CMAC Neural Network With Reduced Storage Requirement  

Oleh:

Ker, Jar-Shone ; Kuo, Yau-Hwang ; Wen, Rong-Chang ; Liu, Bin-Da

Jenis: Article from Journal - ilmiah internasional
Dalam koleksi: IEEE Transactions on Neural Networks vol. 8 no. 6 (1997), page 1545-1556.
Topik: neural network; hardware; implementation; CMAC neural network; storage requirement

Ketersediaan

Perpustakaan Pusat (Semanggi) Nomor Panggil: II36.2 Non-tandon: 1 (dapat dipinjam: 0) Tandon: tidak ada

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Isi artikel

The cerebellar model articulation controller (CMAC) neural network has the advantages of fast convergence speed and low computation complexity. However, it suffers from a low storage space utilization rate on weight memory. In this paper, we propose a direct weight address mapping approach, which can reduce the required weight memory size with a utilization rate near 100 %. Based on such an address mapping approach, we developed a pipeline architecture to efficiently perform the addressing operations. The proposed direct weight address mapping approach also speeds up the computation for the generation of weight addresses. Besides, a CMAC hardware prototype used for color calibration has been implemented to confirm the proposed approach and architecture.

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