VLSI Systolic Arrays for Adaptive Nulling  

Oleh:

Rader, C. M.

Jenis: Article from Bulletin/Magazine
Dalam koleksi: IEEE Signal Processing Magazine vol. 13 no. 4 (1996), page 29-49.
Topik: phased array; VLSI; systolic; arrays; adaptive nulling

Ketersediaan

Perpustakaan Pusat (Semanggi) Nomor Panggil: SS26.1 Non-tandon: 1 (dapat dipinjam: 0) Tandon: tidak ada

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Presents a case study of the design of a computationally intensive system to do adaptive nulling of interfering signals for a phased - array radar with many antenna elements. The goal of the design was to increase the computational horsepower available for this problem by about three orders of magnitude under the tight constraints of size, weight and power which are typical of an orbiting satellite. By combining the CORDIC rotation algorithm, systolic array concepts, Givens transformations, and restructurable VLSI, we built a system as small as a package of cigarettes, but capable of the equivalent of almost three billion operations per second. Our work was motivated by the severe limitations of size, weight and power which apply to computation aboard a spacecraft, although the same factors impose costs which are worth reducing in other circumstances. For an array of N antennas, the cost of the adaptive nulling computation grows as N3, so simply using more resources when N is large is not practical. The architecture developed, called MUSE (matrix update systolic experiment) determines the nulling weights for N = 64 antenna elements in a sidelobe cancelling configuration. After explaining the antenna nulling system, we discuss another DSP computation that might benefit from similar architecture, technology, or algorithms : the solution of Toeplitz linear equations.

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