A Massively Parallel Architecture for Self-Organizing Feature Maps  

Oleh:

Porrmann, M. ; Witkowski, U. ; Ruckert, U.

Jenis: Article from Journal - ilmiah internasional
Dalam koleksi: IEEE Transactions on Neural Networks vol. 14 no. 5 (2003), page 1110-1121.
Topik: ARCHITECTURE; parallel architecture; VLSI design; self-organizing feature maps; hardware accelerator

Ketersediaan

Perpustakaan Pusat (Semanggi) Nomor Panggil: II36.9 Non-tandon: 1 (dapat dipinjam: 0) Tandon: tidak ada

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Isi artikel

A hardware accelerator for self - organizing feature maps is presented. We have developed a massively parallel architecture that, on the one hand, allows a resource - efficient implementation of small or medium - sized maps for embedded applications, requiring only small areas of silicon. On the other hand, large maps can be simulated with systems that consist of several integrated circuits that work in parallel. Apart from the learning and recall of self -organizing feature maps, the hardware accelerates data pre - and post processing. For the verification of our architectural concepts in a real - world environment, we have implemented an ASIC that is integrated into our heterogeneous multiprocessor system for neural applications. The performance of our system is analyzed for various simulation parameters. Additionally, the performance that can be achieved with future microelectronic technologies is estimated.

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