A Compact 3-D VLSI Classifier Using Bagging Threshold Network Ensembles  

Oleh:

Martinez, D. ; Bermak, A.

Jenis: Article from Journal - ilmiah internasional
Dalam koleksi: IEEE Transactions on Neural Networks vol. 14 no. 5 (2003), page 1097-1109.
Topik: DECISION TREES; TECHNOLOGY; 3-D VLSI; network ensembles; packaging technology; decision trees

Ketersediaan

Perpustakaan Pusat (Semanggi) Nomor Panggil: II36.9 Non-tandon: 1 (dapat dipinjam: 0) Tandon: tidak ada

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Isi artikel

A bagging ensemble consists of a set of classifiers trained independently and combined by a majority vote. Such a combination improves generalization performance but can require large amounts of memory and computation, a serious drawback for addressing portable real-time pattern recognition applications. We report here a compact three - dimensional (3D) multiprecision very large - scale integration (VLSI) implementation of a bagging ensemble. In our circuit, individual classifiers are decision trees implemented as threshold networks - one layer of threshold logic units (TLUs) followed by combinatorial logic functions. The hardware was fabricated using 0.7 - µm CMOS technology and packaged using MCM - V micro - packaging technology. The 3D chip implements up to 192 TLUs operating at a speed of up to 48 GCPPS and implemented in a volume of (? × L × h) = (2 × 2 × 0.7) cm3. The 3D circuit features a high level of programmability and flexibility offering the possibility to make an efficient use of the hardware resources in order to reduce the power consumption. Successful operation of the 3D chip for various precisions and ensemble sizes is demonstrated through an electronic nose application.

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