Digital Implementation of Hierarchical Vector Quantization  

Oleh:

Bracco, M. ; Ridella, S. ; Zunino, R.

Jenis: Article from Journal - ilmiah internasional
Dalam koleksi: IEEE Transactions on Neural Networks vol. 14 no. 5 (2003), page 1072-1084.
Topik: Implementation; digital implementation. hierarchical vector; quantization

Ketersediaan

Perpustakaan Pusat (Semanggi) Nomor Panggil: II36.9 Non-tandon: 1 (dapat dipinjam: 0) Tandon: tidak ada

Lihat Detail Induk

Isi artikel

A formal methodology drives the design and realization of a digital very large -scale integration (VLSI) device supporting hierarchical vector quantization (HVQ) in computation - intensive coding applications. The hardware - oriented model - selection approach enhances the Minimum Description Length criterion with circuit - related aspects that allow consistent and efficient design. The resulting model parameters drive the subsequent realization in digital circuitry, which has first been implemented in field - programmable gate array (FPGA) technology to verify its correctness. The eventual VLSI realization results in an HVQ chip providing cost - effective, computationally efficient real - time performances. Real - world applications support the consistency of the vector quantization approach and the effectiveness of the HVQ device.

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