Detail Fundamental design consideration of sampling circuit   Oleh:  Kurihara, Keita ; Kobayashi, Kensuke ; Uemori, Masafumi ; Arai, Miho ; Kobayashi, Haruo Jenis: Article from Proceeding Dalam koleksi: 2016 International Symposium on VLSI Design, Automation and Test (VLSI-DAT) 25-27 April 2016 (ada di IEEE Explore), page 1-4. Fulltext: 07482527.pdf (654.0KB) Isi artikel This paper discusses a theoretical issue of a sampling circuit to maximize SNR while keeping its bandwidth constant, in order to realize a wideband large dynamic range sampling circuit for communication system and measuring instrument applications. We consider two time-constants t1, t2 in the sampling circuit, where is a product of (signal source internal impedance + sampling switch on-resistance) and (hold capacitance), and t2 is a sampling time window (aperture time). We have derived that t2 = 1.50t1 is the condition to maximize SNR keeping the bandwidth constant. We will call it as a strobe sampling circuit when t2 = 1.50t1 is realized. Opini Anda Klik untuk menuliskan opini Anda tentang koleksi ini! Kembali

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