Sense Amplified Differential Gated Flip-Flop For Power Saving & Single Intergity  

Oleh:

Supreeth M. S. ; Umadevi S.

Jenis: Article from Journal - e-Journal
Dalam koleksi: International Journal of Research Science and Management vol. 01 no. 05 (Oct. 2014), page 31-41.
Topik: Clock Skew; Differential Gated; H-clock tree; Resonant clocking; SAGFF clocked flip-flop; NOR Gating
Fulltext: 01_05_Supreeth_Umadevi.pdf (569.01KB)

Isi artikel

The clock distribution network mainly comprises of the clock tree and the flip-flops. The resonant clocking, which drives the clock tree retains a huge potential for an extensive power minimization in the clock distribution network. In addition, the clocked flip-flops, being critical timing elements in the clock distribution circuitry, have become a major contributor to the total power dissipation. Thus, firstly, this paper proposes the design of a novel flip-flop called Sense Amplified Differential Gated Flip Flop (SADGFF). The resonant clock of the design controls the timing of the circuit. This type of semi adiabatic maneuver is proved to reduce the dynamic power dissipation in the proposed design by 26%. Further, the proposed clocked flip-flop achieves a negative setup time, and this factor makes the design extra tolerant to the clock skew and the jitter. This also reduces the D-Q delay, thus refining the timing performance of the flip-flop. Hence, the new clocked energy recovery flip-flop (SADGFF) proves to be a robust, power efficient and performance competent design that eliminates the issues of the existing differential clocked flip-flops. Secondly, this paper also investigates the use of the resonant clock in a Hierarchical clock tree distribution network operating the flip-flops at its leaf node. The advantages of SADGFF clocked flip-flop are validated through exhaustive simulations and comparisons with the SAER and SDER flip-flop structures available in the literature. Furthermore, the post-layout simulations of a typical H-clock tree driving 1024 leaf-cells containing flip-flops have beencarried out. Cadence® EDA tools and the 45nm process technology files have been used to substantiate the merits of the proposed design.

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