Simulation Of An Integrated Architecture For IP-Over-ATM Frame Processing  

Oleh:

Ewert, Peter M. ; Manjikian, Naraig

Jenis: Article from Journal - ilmiah internasional
Dalam koleksi: Simulation vol. 78 no. 4 (Apr. 2002), page 249-257.
Topik: IP-over-ATM; computer networks; processor-memory integration; computer systems; discrete-event simulation
Fulltext: 249.pdf (148.97KB)

Isi artikel

The performance of an integrated architecture for full-duplex IP-over-ATM processing is evaluated through detailed simulation. The architecture combines processing, memory, and multiple directmemory- access engines for single-chip implementation. The simulation models the segmentation and reassembly operations needed to translate IP frames to and from a fixed ATMcell size. A key operation is the insertion of a virtual path and virtual channel identifier (VPI/VCI) into the outgoing ATM cells. Software-based VPI/VCI insertion provides flexibility but requires the on-chip processor to perform this function. Hardware-based VPI/VCI insertion is an optimization that requires one of the directmemory- access engines to perform this task. The two approaches are evaluated through simulated execution of representative control software with detailed modeling of all on-chip components. Results indicate that software-based VPI/VCI insertion supports full-duplex traffic at 475 Mbps on a 500-MHz processor and that hardware-based VPI/VCI insertion supports full-duplex traffic at 560 Mbps on a 500-MHz processor.

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